1. Field of the Invention
The present invention relates to an information processing device having engaged with, in a detachable manner, any one cartridge among a plurality of those each including memory varied in type, and central processing means therein operates in a mode corresponding to the engaged cartridge.
Further, the present invention relates to a storage device corresponding to the cartridge, in a multiplex bus transfer mode, engaged to such information processing device.
Still further, more specifically, the present invention relates to a game system ensuring compatibility among game software, and a game cartridge used for such game system. Compatibility can be successfully ensured by making the game cartridge applicable to both a first game machine of a conventional type and a second game machine higher in performance compared with the first. Such game machine is exemplified by a portable game machine engageable, in a detachable manner, with the game cartridge having a game program stored therein.
2. Description of the Background Art
With reference to FIGS. 21, 22 and 23, described is a conventional information processing system by taking a game system as an example. First, as shown in FIG. 21, a conventional information processing system CGB is mainly composed of a program source 100 and a game machine 200. The program source 100 stores information such as program necessary for the game machine 200 to display images and execute a game, and is structured to be engageable to the game machine 200 in a detachable manner.
The program source 100 is preferably in a form of cartridge including ROM 101, and as required, RAM 102, a clock 104, and a memory bank controller 105. The ROM 101 is exemplarily implemented by nonvolatile memory typified by read-only memory, flash memory, or EE-PROM, and fixedly stores a game program.
The ROM 101 also stores DOT data of an image representing a game character, for example, and as required, a program for data exchange among other game machines (not shown) and a program for ensuring compatibility with any program stored in other program sources (not shown) in the conventional image-display game devices. Hereinafter, the program source 100 is referred to as cartridge. FIG. 23 shows an outer appearance of the cartridge 100.
The RAM 102 is implemented by writable/readable memory typified by random-access memory, and has a region for storing temporary data relevant to the course of the game.
When a memory chunk of the ROM 101 is too large for a CPU in the game machine 200, the memory bank controller 105 divides the memory chunk into a plurality of memory banks, and provides those to the ROM 101 as an upper address based on bank data provided from the CPU. Also to the RAM 102, the memory bank controller 15 accesses in a similar manner. The ROM 101, RAM 102, and memory bank controller 105 are detachably connected to the game machine 200 via a connector 103.
The game machine 200 is mainly composed of an operation key part 202, a Central Processing Unit (CPU) 203, a connector 204, RAM 205, a display controller 206, a liquid crystal display 207, an interface 208, and a connector 209. To the CPU 203, the RAM 205 being working memory for temporarily storing data for game processing, and the display controller 206 are connected. To the display controller 206, the liquid crystal display (LCD) 207 is connected. The CPU 203 is also connected with the connector 209 via the interface 208. The connector 209 is connected to another connector 209 provided to other game machine 200 via a cable for game data exchange with an owner (player) thereof. Here, the CPU 203 is connected to the cartridge 100 via the connector 204.
FIG. 22 shows the outer structure of the information processing system CGB. In the information processing system CGB, the connector 204 (FIG. 21) provided at the rear of the game machine 200 is engaged with the connector 103 (FIG. 21) of the cartridge 100 where memory is located. The operation key part 202 is located on the lower part of the surface (plane) of a housing 201 of the game machine 200. And on the upper part thereof, the liquid crystal display 207 is placed. In the housing 201, a circuit board having the circuit components as shown in FIG. 21 mounted thereon is accommodated.
The operation key 202 includes a direction switch 202a used to move a cursor or direct any character available for the player in desirable directions, an action switch 202b used for action command for the character, a start switch 202c, and a selection switch 202d. 
In such information processing system CGB, the CPU 203 is an 8-bit CPU. Accordingly, the ROM 101, RAM 102, memory bank controller 105, and connector 103 are also structured in a data width of 8-bit specifications. Further, in the information processing system CGB in 8-bit specifications, the ROM 101 and RAM 102 are both driven by 5V. The data width herein means a signal width for all of a data signal, address signal, and control signal exchanged between central processing means such as CPU and memory.
Even in such structured information processing system CGB, the CPU needs to be higher in performance to answer back technology innovation in components typified by the CPU, for example, and users"" increasing demand for higher processing capability. As a result of such technology innovation, the current CPU is differed in processing bit from that in the information processing system CGB. As one example, the CPU currently carries out processing in 32-bit, and accordingly memory system is required to be the one in 32-bit specifications. Under such circumstances, the connectors 103 and 204 are preferably also in 32-bit specifications. Further, as the CPU becomes in higher in performance, a memory space available therefor needs to be increased (also increasing the number of bits of an address signal) in addition to increasing the number of processing bits. For example, the number of bits of an address signal in the CPU 203 of the conventional information processing system CGB is 16, while that in the CPU in the new information processing system is 24 in some cases. In such case, a memory system needs to correspond thereto, and so does a connector, preferably.
Further, with the advancing semiconductor technology, the information processing system of a newly-released type using a cartridge is generally equipped with an integrated circuit (IC) lower in power consumption. As a result, in the new information processing device, semiconductor memory such as ROM and RAM incorporated in the CPU and the cartridge may be driven by different voltage from that for the conventional. For example, the memory system in the information processing system CGB is driven by 5V, while the new-type information processing system is set to be driven by 3.3 V. Therefore, if a cartridge specifically developed for the information processing device low in driving voltage is used in the conventional higher in driving voltage, semiconductor memory in the cartridge suffers due to too much voltage applied thereto, resulting in memory corruption.
However, the conventional information processing system CGB has been used by a lot of users over many years, and various programs have been developed and supplied to the cartridges 100. The issue here is, as described in the foregoing, in accordance with the new-type CPU higher in performance, the new-type information processing device shall adopt the bus transfer mode between the CPU and the memory, the connector in 32-bit specifications, and the memory system driven by 3.3V. Therefore, this new-type information processing device cannot utilize such programs supplied to the cartridges 100 which are huge software resources so far developed for the conventional information processing system CGB.
To get around this type of problem, such technique as disclosed in Japanese Patent Laid-Open Publication No. 11-333144 (99-333144) is well known to keep cartridges compatible with one another. With this technology, a monochrome-version cartridge developed for an information processing device with a monochrome display becomes applicable to another with a color display. As a precondition to realize such application, CPUs in those two information processing devices need to be equal in number of processing bits and the number of bits of an address signal. Another precondition is that those two information processing devices need to be equal in number of connection terminals for connection with the cartridge, and of bit specifications and the number of bits of an address signal in each CPU.
However, if the CPUs in the high- and low-end machines vary in bit specifications and/or number of bits of an address signal, the above technique is not a solution to keep game cartridges compatible with one another.
Recently, in a fixed-type video game machine with a disk drive for optical recording media such as CD-ROM and DVD, for example, even if the recording media differ in type, compatibility has been successfully retained thereamong.
However, even in such video game machine successfully retained compatibility as such, program data has to be first read from the recording medium, and then transferred to a large-capacity RAM in the video game machine for storage. Therefore, this technique is limited in applicability to the cartridge-type game machine.
In order to get around such problem, an information processing device of the present invention (new information processing device) is equipped with both an 8-bit CPU for the conventional information processing system CGB and a 32-bit CPU for the new so as to retain program compatibility (cartridge compatibility) therebetween. With a cartridge for the conventional information processing system CGB inserted, the 8-bit CPU system preferably operates, and the 32-bit CPU system operates responding to a game cartridge for the new information processing device.
For such preferable operation, there needs to be prepared for three subjects mentioned below.
Subject 1) Provide a function of identifying whether memory and a program stored in a cartridge are for the new information processing device or the information processing system CGB. Then, insert a cartridge into the new information processing device so that a voltage appropriate to drive the cartridge is automatically selected before the CPU system of the new information processing device is activated, and then determine which CPU is appropriate for a program stored in the cartridge. In this manner, there needs to switch a voltage to drive the inserted cartridge before the CPU system corresponding thereto is activated.
Subject 2) In order for the new information processing device to be operable with respect to both types of cartridges for the information processing system CGB and the new information processing device, a connector which is an external bus needs to be in 8-bit specifications in accordance with the information processing system CGB. If such connector is 8-bit specifications is used for data transfer between a cartridge and a corresponding CPU system, the number of bits of a data signal to be transferred is differed, 8 or 32 bits, depending on the type of cartridge for the information processing system CGB or the new information processing device. Further, if the CPU in the new information processing device is increased in size of a memory space compared with the conventional processing system CGB, the number of bits of an address signal is increased. Thus, the data width used for data transfer becomes larger to a greater degree. As such, there needs to appropriately switch the bus transfer mode based on the combination of the CPU and external bus differed in data width.
Subject 3) Further, the cartridge only for the new information processing device needs to be provided with a mechanism to deal with the above-described difference in data width, that is, a mechanism to deal with the bus transfer mode in which 32-bit data is transferable via the connector in 8-bit specifications.
As to the subject 1, conventionally, such technology has been disclosed that a slider is moved at the time of connection between an IC card and a connector, and then an incoming signal to the IC card is changed (Japanese Patent Laid-Open Publication No. 8-180149 (96-180149); hereinafter, xe2x80x9cprior art 1xe2x80x9d). Another is a technology of adapter for a memory card (Japanese Patent Laid-Open Publication No. 10-222621 (98-222621); hereinafter, xe2x80x9cprior art 2xe2x80x9d). Therewith, a power-supply voltage for a memory card to be inserted is changed depending on whether the memory card has a concave part or not.
Disclosure made in those prior arts 1 and 2 is changing the voltage or signal supplied to the IC card based on the shape of the IC card (or memory card) and nothing more than that. Therein, the operation of central processing means corresponding thereto is not disclosed at all.
As to the subject 2, the conventional information processing device, game machine, and the like, are provided with a processor and memory such as ROM and RAM. The processor and such memory are connected through a bus, and the processor carries out processing to read data stored in the memory or to write data thereinto. The bus is varied in type including a separate bus which is separated into an address bus and a data bus, and a multiplex bus which is obtained by time-sharing a common bus by address and data (or upper address and lower address, for example), and these two types of bus specifications are selected based on the specifications of the processor or memory.
Herein, a technology of switching the bus between the separate system and the multiplex system is disclosed in Japanese Patent Laid-Open Publication No. 5-204820 (93-204820) (hereinafter, xe2x80x9cconventional technology 1xe2x80x9d) and Japanese Patent Examined Publication No. 6-42263 (94-42263) (hereinafter, xe2x80x9cconventional technology 2xe2x80x9d). These conventional technologies enable a single processor to access both memory of the separate system (hereinafter, xe2x80x9cfirst memoryxe2x80x9d) and memory of the multiplex system (hereinafter, xe2x80x9csecond memoryxe2x80x9d).
However, with such conventional technologies 1 and 2, the number of bits of a data signal outputted to the first memory (or inputted from the first memory) is equal to the number of bits of a data signal outputted to the second memory (or inputted from the second memory). Therefore, those are not applicable to memories varied in type each having different number of bits of data signal.
Also with such conventional technologies 1 and 2, the central processing unit determines, based on an address space, which to access the first memory or the second memory. Consequently, those technologies are applicable only when the central processing unit is connected with the first and second memories simultaneously and fixedly. Those are not applicable if the central processing unit is selectively and exchangeably connected, via a connector, with any one memory among those varied in type (game cartridge, and the like).
On the other hand, with the progression of processor technology, processors equipped in information processing devices and game devices, for example, are started to increase in number of bits for data processing (also the number of bits of an address signal). If the number of bits for data processing is increased in the processors (also, with the larger number of bits of the address signal), memories corresponding thereto are also required to be wider in data width. In many cases, however, using memories narrower in data width may be rewarding, for example, cost-wise.
The information processing devices and game devices, for example, may have several processors varied in number of bits for data processing to ensure the compatibility with software developed in the past. Although the conventional type of game device including several processors is provided with a disk drive for optical recording media, if memory cartridges are used therefor, various types of game cartridges each corresponding to the processors equipped therein are connected via a connector. Here, such connector is preferably available for shared use among those various game cartridges. Therefore, one connector shall be connectable with memories each having different number of bits of data signal (also, each different number of bits of an address signal). In other words, there needs to make a bus available for connecting memories varying in data width.
As to the subject 3, there has been a technology of dealing with two types of memories differed in the number of bits of an address signal, but not yet a technology of dealing with two types of memories each having different number of bits of data signal. Needless to say, no disclosure has been made so far as to memory, in a cartridge having a function of discriminating whether stored memory and program are for the new information processing device or the information processing system CGB.
In order to get around the above-described subject 1, an object of the present invention is to provide an information processing device or a game system capable of discriminating between the new and conventional cartridges (program sources), differing in operation mode, for operation appropriate therefor. To realize such information processing device, before a CPU therein accessing memory in a cartridge engaged thereto, a driving voltage to the memory and the operation mode of the CPU are both changed depending on the engaged cartridge.
In order to get around the above-described subject 2, another object of the present invention is to provide an information processing device or a game system capable of discriminating between the new and conventional cartridges (program sources) differing in operation mode, for operation appropriate therefor. To realize such information processing device, manners of accessing the cartridges are switched depending on the engaged cartridge. Therefore, the cartridge becomes accessible in each different manner determined for each type of memory included therein.
Still another object of the present invention is to provide an information processing device or a game system in which a processor having relatively large number of bits for data processing accesses memory having relatively small number of bits of data.
In order to get around the above-described subject 3, still another object of the present invention is to provide a cartridge (storage device) having a mechanism corresponding to a multiplex bus transfer mode, which allows data transfer relatively large in quantity through a connector relatively narrow in data width. This cartridge is applied to such information processing devices as objected above.
In one preferable embodiment, in order to clear the above-described first subject, an information processing device of the present invention comprises a cartridge discriminator, a voltage supplier, and a central processing unit. This structure helps the information processing device execute processing based on data stored in memory whichever provided in a cartridge engaged thereto in a detachable manner. The cartridge is a first cartridge housing first memory driven by a first voltage or a second cartridge housing second memory driven by a second voltage. The first cartridge is provided with a marker to be discriminated from the second cartridge. Based on the marker, the cartridge discriminator discriminates between the first cartridge and the second cartridge. The voltage supplier supplies the first voltage when the cartridge discriminator identifies the engaged cartridge as being the first cartridge, and supplies the second voltage when identifies as being the second cartridge. The central processing unit becomes operational in a first mode when supplied with the first voltage, and in a second mode with the second voltage. As such, by first identifying the engaged cartridge and then selecting the driving voltage for the memory in the cartridge, the voltage supplied to the memory can be always appropriate. Further, the central processing unit determines its operation mode depending on the selected driving voltage.
In another preferable embodiment, in order to clear the above-described second subject, an information processing device of the present invention comprises an external bus having a first width, a cartridge discriminator, a central processing unit, a first access controller, a second access controller, and a selector. This structure helps the information processing device execute processing based on data stored in memory whichever provided in a cartridge engaged thereto in a detachable manner via the external bus. The cartridge is a first cartridge housing first memory of a first data width or a second cartridge housing second memory of a second data width. The second cartridge is provided with a marker to be discriminated from the first cartridge. Based on the marker, the cartridge discriminator discriminates between the first cartridge and the second cartridge. The central processing unit accesses the memory whichever housed in the engaged cartridge. The first access controller controls the external bus under a normal bus control method, and causes the central processing unit to access the first memory. The second access controller controls the external bus under a different method from the one for the first access controller, and causes the central processing unit to access the second memory. The selector selects the first access controller when the cartridge discriminator identifies the engaged cartridge as being the first cartridge, and selects said second access controller when identifies as being the second cartridge. As such, by identifying the data width of the memory based on the cartridge housing the memory, the information processing device can access the memory in the bus transfer mode appropriate therefor.
In still another preferable embodiment, in order to clear the above-described subject 3, a storage device of the present invention is provided in a first cartridge engageable to an information processing device in a detachable manner, and comprises general-purpose memory for storing data to be executed or utilized in the information processing device, and a multiplex bus converter. Here, the information processing device can be engaged with, in a detachable manner, either the first cartridge wherein an internal bus is of a first data width, or a second game cartridge wherein an internal bus is of a second data width narrower than the first data width. Further, the information processing device comprises a connector of the same data width as the second data width, and a central processing unit which accesses the first cartridge in the multiplex bus transfer mode when connected thereto via the connector, and in the normal bus transfer mode to the second cartridge. The general-purpose memory is of the first data width, and stores data which causes the central processing unit to execute processing. The multiplex bus converter controls address and data exchange between the central processing unit and the general-purpose memory in a time-sharing manner. As such, data exchange is achieved in a manner corresponding to the multiplex bus transfer mode in the information processing device.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.